Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
The Next-Generation Interconnect | Mouser
USB v2.0 Soft PHY and Device Controller
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB IP | Interface IP | DesignWare IP| Synopsys
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP with M31 28nm PHY | audioXpress
TUSB1210 data sheet, product information and support | TI.com
USB 2.0 PHY for SoC Designs | Cadence IP
USB 2.0 Solutions | Arasan Chip Systems
USB 2.0 Device Controller for SoC Designs | Cadence IP
Canovatech - CT25201_PHY
USB 2.0 PHY IP core | Arasan Chip Systems
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
USBPHYC internal peripheral - stm32mpu
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
Having trouble getting USB PHY to work with STM32 : r/embedded
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
USB 3.0 PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
USB Component: USB Device
PCIe/USB/SATA PHY Appilcation example | Renesas
USB 2.0 PHY Verification
